2022
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Fritjof Steinert, Benno Stabernack
Architecture of a Low Latency H.264/AVC Video Codec for robust ML based Image Classification
Journal of Signal Processing Systems, vol. 94, pp. 693–708, January 2022
doi: 10.1007/s11265-021-01727-2
2021
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Philipp Kreowsky, Benno Stabernack
A full-featured FPGA-based pipelined Architecture for SIFT Extraction
IEEE Access, vol. 9, pp. 128564-128573, August 2021
doi: 10.1109/ACCESS.2021.3104387
2018
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Christian Herglotz, Dominic Springer, Marc Reichenbach, Benno Stabernack, Andre Kaup
Modeling the Energy Consumption of the HEVC Decoding Process
IEEE Transactions on Circuits and Systems for Video Technology, vol. 28, no. 1, pp. 217-229, January 2018
doi: 10.1109/TCSVT.2016.2598705
2016
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Jens Brandenburg, Benno Stabernack
Simulation-based HW/SW Co-Exploration of the Concurrent Execution of HEVC Intra Encoding Algorithms for Heterogeneous Multi-Core Architectures
Elsevier Journal of Systems Architecture JSA, December 2016
doi: 10.1016/j.sysarc.2016.12.009 -
Christian Herglotz, Dominic Springer, Marc Reichenbach, Benno Stabernack, Andre Kaup
Modeling the Energy Consumption of the HEVC Decoding Process
IEEE Transactions on Circuits and Systems for Video Technology, vol. 99, no. 99, August 2016
doi: 10.1109/tcsvt.2016.2598705
older
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Benjamin Bross, Heiko Schwarz, Benno Stabernack, Detlev Marpe
Das erste Jahr: HEVC in der Praxis
FKT der Fernseh- und Kinotechnischen Gesellschaft, vol. Heft 08-09/2014, September 2014 -
Denis Engelhardt, Jan Hahlbeck, Jan Möller, Benno Stabernack
FPGA Implementation of a Full HD Real-time HEVC Main Profile Decoder
IEEE Transactions on Consumer Electronics, vol. 62, no. 3, August 2014 -
Martin Werner, Benno Stabernack, Christian Riechert
Hardware Implementation of a Full HD Real-time Disparity Estimation Algorithm
IEEE Transactions on Consumer Electronics, vol. 60, no. 1, February 2014 -
Henryk Richter, Benno Stabernack, Volker Kühn
Architectural Decomposition of Video Decoders by means of an Intermediate Data Stream Format
Springer Journal of Signal Processing Systems, June 2013 -
Heiko Hübert, Benno Stabernack, Frederik Zilly
Architecture of a Low Latency Image Rectification Engine for Stereoscopic 3D HDTV Processing
IEEE Transactions on Circuits and Systems for Videotechnology, vol. 23, no. 6, May 2013 -
C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mähönen, Bart Vanthournout
Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: The 2PARMA Approach
IEEE Micro Special Issue European Multicore Processing Projects, September 2010 -
Heiko Hübert, Benno Stabernack
Profiling-Based Hardware/Software Co-Exploration for the Design of Video Coding Architectures
IEEE Transactions on Circuits and Systems for Videotechnology, Special Issue on Algorithm/Architecture Co Exploration of Visual Computing, December 2009 -
Benno Stabernack, Heiko Hübert, Kai-Immo Wels
A System on a Chip Architecture of an H.264/AVC Coprocessor for DVB-H and DMB Applications
IEEE Transactions on Consumer Electronics, vol. 53, issue 4, May 2007 -
Benno Stabernack
Architekturkonzepte für prozessorbasierte MPEG-Videodecoder mit Schwerpunkt für mobile Anwendungen
Dissertation an der TU-Berlin, Fakultät IV Elektrotechnik und Informatik, December 2004 -
Benno Stabernack
Verfahren und Anordnung zur Ermittlung der Decodierungskomplexität von blockbasiert codierten Videodatenströmen sowie Verwendung dieses Verfahrens und ein entsprechendes Computerprogramm-Erzeugnis zur Regelung der Taktfrequenz
DE-Patentanmeldung, amtliches Aktenzeichen 103 13 149.3, January 2004 -
Benno Stabernack, M. Berekovic, H. J. Stolberg, M. B. Kulaczewski, P. Pirsch, H. Möller, H. Runge, J. Kneip
Instruction Set Extensions for MPEG-4 Video
Journal of VLSI Signal Processing Systems, January 1999 -
G. Junge, Holger Krahn, T. Schleinig, Thorsten Selinger, Benno Stabernack
HDTV durch die digitale Hintertür
Zeitschrift Elektronik, vol. Heft 18/1997, pp. 58, January 1997 -
Benno Stabernack, Maati Talmi
Entwicklung eines MPEG-2 Surround-Sound Dekoders unter Einsatz der Signalprozessoren TMS320C40 von Texas Instruments und MAS3500C von Intermetall
ITG-Fachbericht, Offenbach,Germany, no. 138, January 1996 -
Chr. Stredicke, Jürgen Eindorf, Holger Krahn, Mohsen Owzar, Maati Talmi
Erfahrungen mit FPGAs beim Entwurf von digitalen Schaltungen zur Bildsignalverarbeitung
ITG-Fachbericht, Offenbach,Germany, no. 138, January 1996 -
Martin Hahn, Stefan Wolff, Maati Talmi, Michael Karl
Hardware Implementation of a Motion Compensating Format Converter
Journal Of Electronic Imaging,, vol. 4, no. 3, pp. 270-277, July 1995 -
Thorsten Selinger, M. Block, R. Mudra, Maati Talmi, W. Yan, W. Zhang, M. Zieger
VLSI-Chipsatz für einen MPEG 2 HDTV-Decoder
GME-Fachbericht 15, Mikroelektronik, January 1995
2024
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D. Fey, Benno Stabernack, S. Lankes, M. Pacher, T. Pionteck
Architecture of Computing Systems
37th International Conference on Architecture of Computing Systems, ARCS 2024, Potsdam, Germany, vol. 14842, May 2024
doi: 10.1007/978-3-031-66146-4 -
Philipp Kreowsky, Justin Knappheide, Benno Stabernack
An Approach Towards Distributed DNN Training on FPGA Clusters
37th International Conference on Architecture of Computing Systems, ARCS 2024, Potsdam, Germany, May 2024
doi: 10.1007/978-3-031-66146-4_2
2023
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Steffen Christgau, Dylan Everingham, Florian Mikolajczak, Niklas Schelten, Bettina Schnor, Max Schrötter, Benno Stabernack, Fritjof Steinert
Enabling Communication with FPGA-based Network-attached Accelerators for HPC Workloads
International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC), Denver, USA, November 2023 -
Niklas Schelten, Benno Stabernack, Fritjof Steinert
NAAICE: Network-Attached Accelerators for Heterogenous Computing Environments
29th Workshop GI/ITG Fachgruppe PARS, Aachen, Germany, September 2023 -
Philipp Kreowsky, Justin Knappheide, Benno Stabernack
Challenges using FPGA Clusters for Distributed CNN Training
International Conference on Field-Programmable Logic and Applications (FPL), Gotenburg, Sweden, September 2023 -
Justin Knappheide, Philipp Kreowsky, Benno Stabernack
Demonstrating NADA: A Workflow for Distributed CNN Training on FPGA Clusters
International Conference on Field-Programmable Logic and Applications (FPL), Gotenburg, Sweden, September 2023 -
Fritjof Steinert, Benno Stabernack
FPGA-based Network-attached Accelerators – An Environmental Life Cycle Perspective
ARCS2023: 36th GI/ITG International Conference on Architecture of Computing Systems, Athens, Greece, June 2023
2022
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Michal Stec, Benno Stabernack
Towards an optimal right-turn assistant system to avoid accidents with vulnerable traffic participants
11th Mediterranean Conference on Embedded Computing (MECO), Budva, Montenegro, pp. 1-5, June 2022
doi: 10.1109/MECO55406.2022.9797083 -
Viktor Herrmann, Justin Knappheide, Fritjof Steinert, Benno Stabernack
A YOLO v3-tiny FPGA Architecture using a Reconfigurable Hardware Accelerator for Real-time Region of Interest Detection
Euromirco Conference on Digital Systems Design 2022, DSD2022, 2022
2021
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Fritjof Steinert, Justin Knappheide, Benno Stabernack
Demonstration of a Distributed Accelerator Framework for Energy Efficient ML Processing
31st International Conference on Field-Programmable Logic and Applications (FPL), Dresden, Germany, pp. 386-386, October 2021
doi: 10.1109/FPL53798.2021.00077 -
Benno Stabernack, Fritjof Steinert
Architecture of a Low Latency H.264/AVC Video Codec for robust ML based Image Classification
DASIP 2021: Workshop on Design and Architectures for Signal and Image Processing, Budapest, Ungarn., January 2021
doi: 10.1145/3441110.3441149
2020
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Niklas Schelten, Benno Stabernack, Fritjof Steinert, Anton Schulte
A High-Throughput, Resource-Efficient Implementation of the RoCEv2 Remote DMA Protocol for Network-Attached Hardware Accelerators
International Conference on Field-Programmable Technology (FPT'20), Maui, Hawai, USA , December 2020
pdf: paper.pdf -
Fritjof Steinert, Benno Stabernack, Philipp Kreowsky, Eric Wisotzky
A Hardware/Software Framework for the Integration of FPGA-based Accelerators into Cloud Computing Infrastructures
IEEE International Conference on Smart Cloud (SmartCloud), Washington, ISBN: 978-1-7281-6548-6, November 2020
doi: 10.1109/SmartCloud49737.2020.00014
pdf: 09265948.pdf -
Justin Knappheide, Benno Stabernack, Maximilian Kuhnke
A high throughput MobileNetV2 FPGA implementation based on a flexible architecture for depthwise separable convolution
2020 30th International Conference on Field-Programmable Logic and Applications (FPL), Kopenhagen, ISBN: 978-1-7281-9903-0, August 2020
doi: 10.1109/FPL50879.2020.00053
pdf: 09221517.pdf -
Fritjof Steinert, Benno Stabernack, Niklas Schelten, Anton Schulte
Hardware and Software Components towards the Integration of Network-Attached Accelerators into Data Centers
23rd Euromicro Conference on Digital System Design (DSD), Kranj, Slovenia, Slovenia , ISBN: 978-1-7281-9536-0, July 2020
doi: 10.1109/DSD51259.2020.00033
pdf: 09217847.pdf
2019
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Michal Stec, Benno Stabernack, Viktor Herrmann
Using Time-of-Flight Sensors for People Counting Applications
Conference on Design and Architectures for Signal and Image Processing DASIP 2019, Montréal, Canada, October 2019 -
Michal Stec, Benno Stabernack, Viktor Herrmann
Multi-Sensor-Fusion System for People Counting Applications
Societal Automation Conference SA 2019, Krakow, September 2019
doi: 10.1109/SA47457.2019.8938046
2016
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Jens Brandenburg, Benno Stabernack
Simulation based Analysis of Memory Access Conflicts for Heterogeneous Multi-Core Platforms
12th Workshop on Parallel Algorithms and Systems and Algorithms (PASA), Nürnberg, Germany, April 2016
older
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Benno Stabernack, Jan Möller, Jan Hahlbeck, Jens Brandenburg
Demonstrating an FPGA Implementation of a Full HD Real-time HEVC Decoder with Memory Optimizations for Range Extensions Support
Conference on Design & Architectures for Signal & Image Processing(DASIP2015), Krakow, Poland, September 2015 -
Jens Brandenburg, Benno Stabernack
Exploring the Concurrent Execution of HEVC Intra Encoding Algorithms for Heterogeneous Multi Core Architectures, Electronic Systems and Chip Initiative
Conference on Design & Architectures for Signal & Image Processing (DASIP2015), Krakow, Poland, September 2015 -
Erol Koser, Benno Stabernack
A run-time reconfigurable NoC Monitoring System for performance analysis and debugging support
26. GI/ITG Workshop Parallel -Algorithmen, -Rechnerstrukturen und -Systemsoftware (PARS), University of Potsdam, Germany, May 2015 -
Jan Hahlbeck, Benno Stabernack
A 4k capable FPGA based high throughput binary arithmetic decoder for H.265/MPEG-HEVC
IEEE International Conference on Consumer Electronics - Berlin 2014, Berlin, Germany, September 2014 -
Jens Brandenburg, Benno Stabernack
Memory Access Analysis and Optimization of a Parallel H.264/SVC Decoder for an Embedded Multi-Core Platform
Electronic Systems and Chip Initiative, Conference on Design and Architectures for Signal and Image Processing (IEEE DASIP2013), Cagliari, Italy, October 2013 -
Benjamin Bross, Valeri George, Mauricio Alvarez-Mesa, Tobias Mayer, Chi Ching Chi, Jens Brandenburg, Thomas Schierl, Detlev Marpe, Ben Juurlink
HEVC Performance and Complexity for 4K Video
IEEE International Conference on Consumer Electronics - Berlin 2013, Germany, pp. 44-47, September 2013 -
A. Bartzas, P. Bellasi, Jens Brandenburg, W. Fornaciari, I. Koutras, G. Massari, G. Palermo, E. Paone, C. Silvano, D. Soudris, S. Xydis, V. Zaccaria
Cooperative Design Space Exploration and Run-Time Resource Management for Application Adaptivity on Multi-Core Platforms: A Networked Video Surveillance Use Case
Proceedings of the DATE 2013 International Conference, DEPCP2013, WORKSHOP: Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools and Applications, Grenoble, France, March 2013 -
Jens Brandenburg, Benno Stabernack
Performance and Memory Access Analysis for Embedded Multi-Core Media Signal Processing Platforms using NoCTrace
Proceedings of 8th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) / Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms, Berlin, Germany, January 2013 -
Henryk Richter, Benno Stabernack, Volker Kühn
Architectural Decomposition of Video Decoders for Many Core Architectures
Electronic Systems and Chip Initiative, Conference on Design and Architecture for Signal and Image Processing (IEEE DASIP2012), Karlsruhe, Germany, October 2012 -
Benno Stabernack, Jens Brandenburg
A Novel Profiling Methodology for Many-Core Simulation Models aiming HW/SW Co-Optimization
Proceedings of the DATE 2012 International Conference, DEPCP2012, WORKSHOP: Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools and Applications, Dresden, Germany, March 2012 -
Jens Brandenburg, Benno Stabernack
A Generic and Non-Intrusive Profiling Methodology for SystemC Multi-Core Platform Simulation Models
Proceedings of ARCS 2012 - Architecture of Computing Systems Conference, Munich, Germany, February 2012 -
Benno Stabernack, Jens Brandenburg
NoCTrace - A Non Intrusive System Level Architecture Exploration Tool for Network on Chip Architectures
Proceedings of 7th International Conference on High-Performance and Embedded Architectures and Compilers (HiPEAC) / Workshop on Design Tools and Architectures for Multi-Core Embedded Computing Platforms, Paris, France, January 2012 -
C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J.M. Zins, H. Hubert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mahonen, B. Vanthournout
Parallel Paradigms and Run-time Management Techniques for Many-core Architectures: The 2PARMA Approach
Proceedings of IEEE 9th International Conference on Industrial Informatics (INDIN'2011), Caparica, Lisbon, Portugal, July 2011 -
C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, E. Speziale, D. Melpignano, J.M. Zins, H. Hubert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, I. Anagnostopoulos, A. Bartzas, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mahonen, B. Vanthournout
Parallel programming and Run-time Resource Management Framework for Many-core Platforms: The 2PARMA Approach
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'2011), Montpellier, France, June 2011 -
Cristina Silvano, William Fornaciari, David Siorpaes, Benno Stabernack, Chantal Couvreur, Dimitrios Soudris, Torsten Kempf, Bart Vanthournout
2PARMA: PARallel PAradigms and Runtime MAnagement techniques for Many-core Architectures
DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2011), Grenoble, France, March 2011 -
Benno Stabernack, Jens Brandenburg
NoCTrace - A System Level Architecture Exploration Tool for Network on Chip Architectures
DATE Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications (DEPCP 2011), Grenoble, France, March 2011 -
Heiko Hübert, Benno Stabernack
Energy Analysis of Embedded Software Based on a Cycle-Accurate Processor Power Model
Proceedings of the IEEE Symposium on Industrial Electronics and Applications (ISIEA 2010),Penang, Malaysia, October 2010 -
Benno Stabernack
Programming Multicore Architectures: The 2PARMA Approach
Intel European Research and Innovation Conference 2010 (ERIC 2010) Braunschweig, Germany, September 2010 -
C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Siorpaes, H. Hübert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, H. Meyr, J. Ansari, P. Mähönen, B. Vanthournout
2PARMA: Parallel Paradigms and Run-time Management Techniques for Many-Core Architectures
IEEE Computer Society, Annual Symposium on VLSI 2010, Lixouri, Kefalonia, Greece, July 2010 -
Thomas Wirth, Lars Thiele, Thomas Haustein, Jens Brandenburg, Benno Stabernack
Scalable Video Broadcasting Trials in 4G Cellular Deployments
Proceedings of the Future Network Mobile Summit, Florence, Italy, June 2010 -
Henryk Richter, Benno Stabernack, Erika Müller
Adaptive multithreaded H.264/AVC decoding
Asilomar Conference on Signals, Systems, and Computers, Monterey, California, USA, November 2009 -
Benno Stabernack, Heiko Hübert, Jens Brandenburg, Jan Möller
An Experimental Mobile Terminal for Scalable Video Coding Applications using a H.264/AVC Decoder SOC
Proceedings of 13th IEEE International Symposium on Consumer Electronics, Mielparque-Kyoto, Kyoto, Japan, May 2009 -
Heiko Hübert, Benno Stabernack
Power Modeling of an Embedded RISC Core for Function-Accurate Energy Profiling
ITG Workshop, Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen, Berlin, Germany, March 2009 -
Henryk Richter, Benno Stabernack
Generic Algorithms for Motion Compensation and Transformation
IS&T/SPIE´s 20th Annual Symposium Electronic Imaging, Conference: Real-Time Image Processing 2008, Proceedings of SPIE, San Jose, California, USA, pp. 27-30, January 2008 -
Heiko Hübert, Benno Stabernack, Kai-Immo Wels
Performance and Memory Profiling for Embedded System Design
Proceedings IEEE Second International Symposium on Industrial Embedded Systems (SIES 2007), Lisbon, Portugal, July 2007 -
Benno Stabernack, Kai-Immo Wels, Heiko Hübert
A Video Coprocessor for Mobile Multi Media Signal Processing
Proceedings of the Eleventh IEEE International Symposium on Consumer Electronics (ISCE 2007), Dallas, Texas, USA, June 2007 -
Benno Stabernack, Heiko Hübert, Kai-Immo Wels
A Companion Chip for H.264/AVC Video Processing
Proceedings GSPx 2006, Santa Clara, California, USA, October 2006 -
Benno Stabernack, Heiko Hübert, Kai-Immo Wels
Terminal Architectures for DVB-H
Proceedings GSPx-TV to Mobile 2006, Amsterdam, Netherlands, March 2006 -
Benno Stabernack, Heiko Hübert, Kai-Immo Wels
A H.264 Video Coprocessor for Mobile DVB-H Terminals
IEEE International Conference on Consumer Electronics ICCE 2006, Las Vegas, Nevada, USA, January 2006 -
Benno Stabernack, Rainer Großmann
Design und Implementierung eines mobilen Endgerätes für DVB-H Empfang
Proceedings Dortmunder Fernsehseminar, ITG/FKTG Fachtagung, Dortmund, Germany, October 2005 -
Henryk Richter, Benno Stabernack
Realtime Optimization Techniques for Processor based H.264 Intra Frame Compression
Proceedings GSPx 2005, Santa Clara, California, USA, October 2005 -
Benno Stabernack, Henryk Richter
Media Processor Architectures for Mobile DVB-H Terminals
Proceedings GSPx 2005, Santa Clara, California, USA, October 2005 -
Benno Stabernack, Henryk Richter
Instruction Set extensions for Mobile Video Applications on Embedded RISC Processors
IEEE International Conference on Consumer Electronics ICCE 2005, Las Vegas, NV, USA, January 2005 -
Benno Stabernack, Henryk Richter, Erika Müller
A SIMD Instruction Set Architecture optimized for H.264 video Processing
Picture Coding Symposium (PCS'04), San Francisco, CA, USA, December 2004 -
Heiko Hübert, Benno Stabernack, Henryk Richter
Tool-Aided Performance Analysis and Optimization of an H.264 Decoder for Embedded Systems
8th IEEE International Symposium on Consumer Electronics (ISCE 2004) , Reading, UK, ISBN: 0-7803-8527-6 , September 2004
doi: 10.1109/ISCE.2004.1375977 -
Heiko Hübert, Benno Stabernack, Henryk Richter
Tool-Aided Performance Analysis and Optimization of Multimedia Applications
Second Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia 2004), Stockholm, Sweden, September 2004 -
Benno Stabernack, Henryk Richter, Erika Müller
Evaluating and Implementing H.264 for Embedded and Mobile Streaming Applications
SPIE, Optical Science and Technology, SPIE's 48th Annual Meeting, Applications of Digital Image Processing, San Diego, California, USA, vol. 5203, November 2003
doi: 10.1117/12.512609 -
Benno Stabernack, Kai-Immo Wels, Corina Scheiter, Rainer Steffen, Markus Zeller, Rudi Knorr
A System for QoS enabled MPEG-4 Video Transmission over Bluetooth for Mobile Applications
IEEE International Conference on Mulitmedia and Expo ICME 2003, Baltimore, Maryland, USA, July 2003 -
Benno Stabernack, Gerd von Cölln
An MPEG-4 Video Codec SOC for Mobile Multi Media Applications
IEEE International Conference on Consumer Electronics ICCE 2003, Los Angeles, California, USA, June 2003 -
Benno Stabernack, Thomas Schierl, Henryk Richter, T. Rathgen
Using RTSP/RTP and MPEG-4 for streaming and bi-directional mobile multimedia communication
IEEE International Symposium on Consumer Eletronics ISCE 02, Illmenau, Germany, September 2002 -
Benno Stabernack, Martin Köhler, Matthias Reißmann, Gerd von Cölln
A processor based system on a chip design für mobile multi media applications
IEEE International Symposium on Consumer Eletronics ISCE 02, Illmenau, Germany, September 2002 -
Benno Stabernack, Henryk Richter
High Quality Multimedia Streaming using MPEG-4 Technology
6th World Multiconference on Systemics, Cybernetics and Informatics (SCI 2002), Orlando, Florida, USA, July 2002 -
Benno Stabernack, Henryk Richter
A Multi Media Streaming Framework for Mobile Applications, A first Approach
12 th International Packetvideo Workshop (PV2002), Pittsburgh PA, USA, April 2002 -
Henryk Richter, Aljoscha Smolic, Benno Stabernack, Erika Müller
Real Time Global Motion Estimation for an MPEG-4 Video Encoder
Picture Coding Symposium (PCS'01), Seoul, Korea, April 2001 -
Benno Stabernack
Real time implementation of an DSP-based MPEG-4 Videodecoder
ICSPAT, Orlando, Florida, USA, October 1999 -
Martin Hahn, Christian Huck, Kathrin Rümmler, Maati Talmi, Stefan Wolf
Single-Chip Videokonverter für Multimedia-Displays
8. ITG-Fachtagung Dortmunder Fernsehseminar, Dortmund, Germany, September 1999 -
Benno Stabernack
Echtzeitimplementierung eines MPEG-4 Videodecoders basierend auf dem digitalen Signalprozessor TMS320C6201 von Texas Instruments
8. Dortmunder Fernsehseminar, Dortmund, Germany, September 1999 -
Ulrich Höfker, H. Krahn, Ralf Schäfer, Peter Stammnitz, Maati Talmi
HiPEG – A Single Chip MPEG-2 HDTV Decoder and HiBOX, a DVB Compliant HDTV Decoder Box
International Broadcast Convention (IBC'98), Amsterdam, Netherlands, pp. 185-189, September 1998 -
M. Berekovic, G. Meyer, Yong Guo, P. Pirsch, Benno Stabernack
A Multimedia RISC Core for efficient Bitstream Parsing and VLD
SPIE, Photonics West '98 Electronic Imaging, Multimedia Hardware Architectures, San Jose, USA, vol. 3311, pp. 131-142, January 1998
doi: 10.1117/12.304665 -
Martin Hahn, Christian Huck, M. Braun, Jens-Rainer Ohm, Maati Talmi
Single-Chip Motion-Compensated Video Format Converter for Multimedia Displays
Picture Coding Symposium PCS97, Berlin, Germany, September 1997 -
Benno Stabernack
A Flexible MPEG-2 Audio Decoder and Transport Stream Interface based on TMS 320C40 and ITT MAS3500C
Proceedings of the European Workshop on Image Analysis and Coding for TV, HDTV and Multimedia Applications, Rennes, France, February 1996 -
Benno Stabernack, Maati Talmi
Entwicklung eines MPEG-2 Surround Sound Dekoders unter Einsatz der Signalprozessoren TMS320C40 von Texas Instruments und MAS3500C von Intermetall
ITG-Fachtagung, Chemnitz, Germany, ISBN: 3-8007-2171-6, January 1996 -
Holger Krahn, Ch. Stredicke, Maati Talmi
Erfahrungen mit FPGAs in der digitalen Bildsignalverarbeitung
2. GI/ITG-Workshop für Anwenderprogrammierbare Schaltungen, Karlsruhe, Germany, June 1995 -
S. Fazelpour, B. Bölike, H. Reichl, Maati Talmi
Design und Realisierung eines Multi-Chip-Moduls als Bewegungsschätzer für HDTV-Anwendungen
SMT'95, Electronic Systems & Solutions, Hybrid'95, Nürnberg, Germany, May 1995 -
Christian Stoffers, B. Bölike, S. Fazelpour, H. Reichl, Maati Talmi
Systementwurf und Einsatzumgebung eines Multi-Chip-Moduls als Bewegungsschätzer für HDTV-Anwendungen
SMT'95, Electronic Systems & Solutions, Hybrid'95, Nürnberg, Germany, May 1995 -
S. Fazelpour, B. Bölike, H. Reichl, Maati Talmi
Design und realisierung eines Multi-Chip-Moduls als Bewegungsschätzer für HDTV-Anwendungen
SMT’95, Electronic Systems & Solutions, Hybrid, Nürnberg, Germany, May 1995 -
Stefan Wolf, Maati Talmi, Christian Stoffers, Martin Hahn, M. Braun
Key Components for Format Conversion
European Workshop on Image Format Conversion and Transcoding, Berlin, Germany, March 1995 -
Stefan Wolf, Maati Talmi, Martin Hahn, Jürgen Eindorf, Klaus Böttcher, M. Braun, J. Dressler, C. Heinelt, R. Horn, Michael Karl, Kathrin Rümmler, Chr. Stredicke
Motion Compensated 4:2:2 to HDI Format Converter
Proceedings of European Workshop and Exhibition on Image Format Conversion and Transcoding, Berlin, Germany, March 1995 -
Benno Stabernack, C. Heinelt, Maati Talmi, W. Sinnhöfer
A Flexible MPEG 2 Audio Decoder and Transport Stream Interface Based on TMS320C40 and ITT MAS3500C
International Conference on Signal Processing and Applications (ICSPAT), Massachusetts, Boston, Massachusetts, USA, January 1995 -
R. Horn, Maati Talmi
Design of a Modular Multi-DSP-System for Hierarchical Motion Estimation in combination with Customized Processors
International Conference on Signal Processing and Applications (ICSPAT), Massachusetts, Boston, Massachusetts, USA, January 1995 -
P. Kanold, M. Block, Thorsten Selinger, Maati Talmi, W. Yan, W. Zhang
Test and Monitoring of an HDTV MPEG-2 Video Decoder using the TMS320C40
International Conference on Signal Processing and Applications (ICSPAT), Dallas, Texas, USA, October 1994 -
Thorsten Selinger, M. Block, P. Kanold, Maati Talmi, W. Yan, W. Zhang, M. Zieger
Chipset for a Single-Board MPEG-2 SSP@H-1440L HDTV-Decoder
Proceedings of International Workshop on HDTV '94, Turin, Italy, October 1994 -
Michael Karl, Maati Talmi
TMS320C40 Applications for Real-Time Image Processing: Communication Port Interface Designs for Synchronized Data Transfer
International Conference on Signal Processing and Applications (ICSPAT), Dallas, Texas, USA, October 1994 -
M. Ludwigs, R. Orglmeister, Michael Karl, Maati Talmi
A Scalable Multiprocessor System for Real Time Image Processing Applications based on DSP 96002
International Conference on Signal Processing and Applications (ICSPAT), Dallas, Texas, USA, October 1994 -
Maati Talmi, M. Block, P. Kanold, Thorsten Selinger, M. Schubert, W. Yan, W. Zhang, M. Zieger
VLSI realization of a hierarchical MPEG-2 TV&HDTV decoder
Visual Communications and Image Processing '94, SPIE, Chicago, Illinois, USA, pp. 1734-1741, September 1994 -
Stefan Wolf, Maati Talmi, M. Block, M. Braun
VLSI-Komponenten für die Bewegungsschätzung bei der HDTV-Hybridcodierung und Formatkonversion
6. ITG-Fachtagung Mikroelektronik und Informationstechnik, Berlin, Germany, March 1994 -
Martin Hahn, Stefan Wolf, Maati Talmi, Michael Karl
A Real Time Motion Compensating TV to HDTV Converter
Conference of Visual Communications and Image Processing (VCIP), Chicago, Illinois, USA, January 1994 -
Benno Stabernack, C. Heinelt, W. Sinnhofer
A Flexible MPEG-2 Audio Decoder and Transport Stream Interface Based on TMS320C40 and ITT MASC3500C
5th International Conference on Signal Processing Applications & Technology (ICSPAT '94), Dallas, Texas, January 1994 -
Stefan Wolf, Maati Talmi, Michael Karl
A Real Time Motion Compensating Converter from TV to HDTV
International Workshop on HDTV ' 93, Ottawa, Canada, October 1993 -
S. Wolf, Maati Talmi, Michael Karl
Realisierung eines bewegungskompensierenden TV zu HDTV-Konverters Für Echtzeitanwendungen
5. ITG-Fachtagung Dortmunder Fernsehseminar, Dortmund, Germany, September 1993 -
Th. Selinger, Maati Talmi, W. Yan, W. Zhang
Konzeption und VLSI-Realisierungen für einen hierarchischen TV/HDTV Decoder
5. ITG-Fachtagung Dortmunder Fernsehseminar, Dortmund, Germany, September 1993
2024
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Viktor Herrmann, Philipp Kreowsky, Benno Stabernack, Jonathan Pfaff, Heiner Kirchhoffer, Christian Helmrich, Sophie Pientka, Christian Rudat, Heiko Schwarz, Detlev Marpe, Thomas Wiegand
Demonstrator for Fraunhofer HHI’s response to the Call for Proposals on the compression of biomedical waveform data
75th Meeting, Kemer, TR, Document VCEG-BW13, November 2024
2019
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Adarsh Krishnan Ramasubramonian, G. Van der Auwera, T. Hsieh, V. Seregin, L. Pham Van, M. Karczewicz, Santiago De-Luxán-Hernández, Benjamin Bross, Tung Nguyen, Valerie George, Benno Stabernack, Heiko Schwarz, Detlev Marpe, Thomas Wiegand
CE3-1.6: On 1xN and 2xN subblocks of ISP
Document JVET-O0106 of the JVET, 2019 -
Santiago De-Luxán-Hernández, Benjamin Bross, Tung Nguyen, Valeri George, Benno Stabernack, Heiko Schwarz, Detlev Marpe, Thomas Wiegand
Non-CE3: ISP with independent sub-partitions for certain block sizes
Document JVET-N0372 of the JVET, 2019 -
Santiago De-Luxán-Hernández, Benjamin Bross, Tung Nguyen, Valerie George, Benno Stabernack, Heiko Schwarz, Detlev Marpe, Thomas Wiegand
Ristriction of the maximum CU size for ISP to 64x64
Document JVET-N0308 of the JVET, 2019 -
Heiner Kirchhoffer, Christian Bartnik, Tobias Hinz, Jan Stegemann, Paul Haase, Stefan Matlage, Benno Stabernack, Heiko Schwarz, Detlev Marpe, Thomas Wiegand
CE5: Report of software throughput analysis for CE5.2 by HHI
Document JVET-M0762 of the JVET, 2019 -
Benno Stabernack, T. Hsieh
CE5: Report of subtest 3 on complexity and throughput aspects for hardware
Document JVET-M0759 of the JVET , 2019 -
Heiner Kirchhoffer, Christian Bartnik, Paul Haase, Tobias Hinz, Stefan Matlage, Benno Stabernack, Jan Stegemann, Detlev Marpe, Heiko Schwarz, Thomas Wiegand
CE5-related: Minor optimizations for increasing the throughput of CE5.1.5 and CE5.1.6
Document JVET-M0389 of the JVET , 2019
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Benno Stabernack, Detlev Marpe, Thomas Wiegand
H.264/AVC Real-Time Video Decoder Demonstration
Pattaya, Thailand, Joint Video Team, Doc. JVT-G042, March 2003 -
Benno Stabernack, et.al
Generically optimized VM7 compatible MPEG-4 video decoder
M2813, Conribution to ISO/IEC JTC1/SC29/WG11, January 1998 -
Benno Stabernack, et al
Set Of Complexity Profiles For MPEG-4 VM-8- And VCD-V08-Compliant Video Decoder Implementations
M3182, Contribution to ISO/IEC JTC1/SC29/WG11, January 1998
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Heiko Hübert, Benno Stabernack
Using Configurable CPU Cores for Demanding Mobile Multimedia Applications
Proceedings ConfigCon 2006, Santa Clara, California, USA, October 2006, Invited Talk -
Heiko Hübert, Benno Stabernack
Using Configurable CPU Cores for Demanding Mobile Multimedia Applications
Proceedings ConfigCon 2006, Taipei, Taiwan, February 2006, Invited Talk -
Martin Hahn, Maati Talmi, T. Weber
Multistandard Audio/Video-Prozessor MAViP
ITG-Fachtagung Elektronische Medien (Dortmunder Fernsehseminar), Dortmund, Germany, September 2003 -
Thorsten Selinger, Maati Talmi, W. Yan, W. Zhang
Konzeption und VLSI-Realisierungen für einen hierarchischen TV/HDTV Decoder
5. Dortmunder Fernsehseminar, ITG/FKTG, Universität Dortmund, October 1993
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C. Silvano, W. Fornaciari, S. Crespi Reghizzi, G. Agosta, G. Palermo, V. Zaccaria, P. Bellasi, F. Castro, S. Corbetta, A. Di Biagio, E. Speziale, M. Tartara, D. Melpignano, J.-M. Zins, D. Siorpaes, H. Hubert, Benno Stabernack, Jens Brandenburg, M. Palkovic, P. Raghavan, C. Ykman-Couvreur, A. Bartzas, S. Xydis, D. Soudris, T. Kempf, G. Ascheid, R. Leupers, H. Meyr, J. Ansari, P. Mahonen, B. Vanthournout
2PARMA: Parallel Paradigms and 3 Run-time Management Techniques for Many-Core Architectures
VLSI 2010 Annual Symposium, Selected Papers, Editors: N. Voros, A. Mukherjee, N. Sklavos, K. Masselos, M. Huebner, Lecture Notes in Electrical Engineering, Springer Verlag, Netherlands, vol. , pp. 65-79, August 2011 -
Benno Stabernack, Heiko Hübert, Kai-Immo Wels
Hardware and Software Architectures for Mobile Multi Media Signal Processing
Handbook of Mobile Broadcasting: DVB-H, DMB, ISDB-T and MediaFLO, Auerbach Publications, Taylor & Francis Group, CRC Press, Boca Raton, FL, USA, pp. 95-132, April 2008
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Heiko Hübert
MEMTRACE: A memory, performance and energy profiler targeting RISC-based embedded systems for dataintensive applications
Technische Universität, Fakultät IV - Elektrotechnik und Informatik, Berlin, Germany, January 2009 -
Benno Stabernack
Architekturkonzepte für prozessorbasierte MPEG Videodecoder mit Schwerpunkt für mobile Anwendungen
Technische Universität Berlin, Fakultät IV - Elektrotechnik und Informatik, Berlin, Germany, September 2004