Competence for 3D Content Creation
The Fraunhofer Heinrich Hertz Institute research groups „Immersive Media & 3D-Video“ and „Embedded Systems“ are the one-stop address for 3D content creation. Algorithms, software and hardware to process multiple video streams are combined to develop new solutions for 2D, 3D and beyond.
- Setup, calibration and capture using multi-view video systems
- Offline and real-time 3D video analysis and disparity estimation
- Rendering of content for stereo, autostereo and immersive multi-projection systems
- Co-design of hardware, software and the overall system architecture
- Architecture approaches are addresed from hardware accelerated coprocessors up to many-core platforms
Hybrid 3D
A system based on Trifocal Depth Capture is providing a way towards reliable depth maps with only minimal additional effort on set compared to 2D. During postproduction dense depth maps are estimated allowing rendering additional virtual views with an individual virtual camera baseline optimally adjusted for the planned screening scenario.
STAN – Stereoscopic Analyzer
The Stereoscopic Analyzer STAN is a system for production of perfect stereo 3D. STAN combines real-time image analysis with intelligent automated tools. An intuitive graphical user interface assists camera operators and production staff in shooting technically correct stereo for all 3D genres including live events.
AFX Plug-in Suite for Stereo-to-Multiview Conversion
Fraunhofer HHI provides an easy-to-use Adobe After Effects (AFX) plug-in solution for high-quality 3D content conversion from live-action stereo footage.
Real-time Stereo-to-Multiview Conversion – IP core and FPGA reference implementation for depth estimation
Real-time stereo-to-multiview conversion allows playback of 3D Blu-ray content or any other stereoscopic 3D video content on autostereoscopic displays. Costly offline conversion is no longer needed and personal 3D viewing preferences can be adjusted on-the-fly. Depth estimation, the heart of stereo-to-multiview conversion, is now available as a pure hardwired IP core suited for FPGA and ASIC implementation. For evaluation purposes a reference FPGA implementation can be provided.
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