Digital signal processing (DSP) is a key technology for mitigation of transmission impairments and maximization of channel capacity in communication systems. Real-time implementation of DSP algorithms enables a fast and practical proof of concept under realistic conditions. The ready-to-use IP Cores of the Fraunhofer HHI support your development of high-speed communication systems. All IP Cores are fully customizable to your application.
The IP cores are regularly used in HHI’s custom prototype development. Their performance has been tested and verified for various state-of-the-art FPGAs in multiple applications.
Below are our IP cores available for purchase. Please contact us for detailed data sheets, documentation, customization options and pricing. If you require any other IP core, do not hesitate to contact us.
Fast Fourier Transform
Short description
The Fast Fourier Transform (FFT) IP Core from the Fraunhofer Heinrich Hertz Institute is a customizable parallel FFT implementation. The core was specifically designed to achieve very high throughput while saving as many resources as possible at the same time. The core is highly configurable in terms of resolution (bit-width), parallelization and FFT size.
Features
- Platform-independent
- Low-resource usage
- Configurable degree of parallelization
- Configurable FFT size
- Configurable data (and twiddle factor) precision
- Dynamic change between FFT and IFFT operation
- Continuous data processing (no idle time)
Example configuration
- 1024 point FFT
- 64 complex inputs
- 9-bit input width
- 19-bit output width
- 11-bit twiddle factor width
Low Latency 10G Ethernet MAC
Short description
The 10G Ethernet MAC IP Core from the Fraunhofer Heinrich Hertz Institute is a low latency Ethernet Media Access Controller (MAC). It is designed to the IEEE802.3-2008 specification. The core was specifically designed to have the lowest possible latency and to save as many resources as possible at the same time. This makes it ideal for low-latency applications such as e.g. high-frequency trading.
Features
- Platform independent core
- Low Latency, 19.2ns@64-Bit@156.25MHz
- AXI4-Stream protocol support on client transmit and receive interface
- Low resource usage
- Deficit Idle Count mechanism to ensure full data rate
- Padding of short frames (<64 byte)
- Support for VLAN tagged frames
- Promiscuous mode support
- Generation and checking of CRC-32 at full line rate
- Optional user defined maximum frame length up to 64 kb or complete disabling of frame length check
- Customization through configuration vector to trade resources for functionality
Feed-Forward Clock Recovery
Short description
The feed-forward clock recovery performs clock phase and clock frequency recovery for pulse shaped signals (e.g. root raised cosine pulse shape with roll-off factor 0.5). The architecture is fully feed-forward using a Lee timing error estimator which controls a sample dropping unit and interpolators.
Features
- Digital clock recovery scheme
- feed-forward architecture
- no feedback path to ADC required
- based on sample dropping and interpolation
Feed-Forward Carrier Phase Recovery
Short description
The feed-forward carrier phase recovery IP-core performs carrier phase recovery for mPSK signals. It is based on the Viterbi & Viterbi mth power algorithm and is implemented in a scalable blockwise parallel processing architecure. Optionally, differential decoding can be performed after carrier phase recovery.
Features
- Viterbi & Viterbi mth power algorithm
- Suitable for M-PSK
- Scalable blockwise, parallel processing architecture
- Differential decoding included
Channel Demultiplexer
Short description
The weighted overlap add (WOLA) channelizer efficiently performs channel separation, matched filtering, down-conversion to baseband and decimation. For real valued input signals the IP core generates complex valued output signals.
Features
- weighted overlap add (WOLA) channelizer
- Simultaneous frequency band separation, matched filtering, down-conversion to baseband and decimation.
Multi-Format Mapper
Short description
The multiformat mapper maps the input binary data into complex symbols using the specified modulation format. The mapper supports M-ary phase-shift keying (M-PSK), M-ary quadrature amplitude modulation (M-QAM) and M-ary pulse amplitude modulation (M-PAM) formats.
Features
- Supports multiple modulation formats (M-PSK, M-QAM, M-PAM)
- User-defined constellations
- User-defined output format
OFDM Transmitter
Short description
The high-speed OFDM transmitter is an IP core that performs the required digital signal processing to generate flexible OFDM signals with gross data rates up to 64 Gb/s. The IP core is optimally designed to be implemented in a single FPGA chip that can interface two high-speed digital to analog converters (DAC). The generated OFDM signal consists of two independent outputs for the in-phase (I) and quadrature (Q) paths of 5 bits resolution that can be sampled at up to 16 GS/s. The control interface to synchronize the DACs is an incorporated OFDM feature.
Features
- Up to 64 Gb/s gross data rate
- Up to 1024 subcarriers (1024 point IFFT)
- Internal random data generation
- Free programmable bit loading mask
- Free programmable training sequence
- Periodic training sequence insertion
- Free programmable power coefficients for power loading
- Cyclic prefix insertion
- 2x8 GHz output signal baseband bandwidth
- Interface for two high-speed digital to analog converter (DAC)
Adaptive Time-Domain Equalizer
Short description
The adaptive 2x2 MIMO time-domain equalizers operates on complex input/output values and may be used for polarization demultiplexing in coherent mPSK receivers. The filter is updated periodically by employing the constant modulus algorithm (CMA). For signal acquisition, a constrained update based on the unitary matrix criterion may be employed.
Features
- Polarization demultiplexing for coherent QPSK and mPSK receivers
- 2x2 MIMO operation
- FIR filter tap update by constant modulus algorithm (CMA)
- Constrained update mode for stable acquisition
- Unconstrained update mode for tracking
Data-Aided Single-Carrier Equalizer
Short description
The data-aided single-carrier equalizer is an IP core that performs the required digital signal processing for the carrier frequency recovery and the 2x2 multiple-in-multiple-out (MIMO) equalization of dual-polarization signals with arbitrary modulation format in a coherent receiver. It expects to find a predefined, periodically inserted header in the received signal which is used for frequency-offset estimation (FOE) and channel estimation.
Features
- Fast and stable channel estimation based on pilot symbols
- Applicable for burst-mode transmission
- Frame synchonization
- Carrier frequency recovery
- Frequency-domain equalization
- Arbitrary payload modulation format